GE IS420UCSCH2A-C-V0.1-A

Description

GE IS420UCSCH2A-C-V0.1-A

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IS420UCSCH2A-C-V0.1-A From this timing diagram, it can be seen that SCL is very important, and which clock edge does what is determined. For example, the first 7 must be addresses, the 8th must be read/write flags, data transmission must be 8-bit, an ACK signal must be received, and so on.

IS420UCSCH2A-C-V0.1-A requires a master device responsible for initiating requests and controlling clocks; Others are slave devices that identify and respond to master device requests through device ID addresses. The master and slave devices need to take turns controlling SDA. At first, I didn’t understand this point and simply added I2C data code. Then, I used an oscilloscope to measure the SDA and SCL pins, but I could only find some messy waveforms without the expected effect. Later, after connecting the slave device and writing code on both sides, they responded to each other, and only then did they see the waveform on the oscilloscope.

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