216DB61 HESG324063R100J | ABB| Dual redundant network cable connection

Description

216DB61 HESG324063R100J | ABB| Dual redundant network cable connection

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In the above 216DB61 HESG324063R100J , according to the requirements of Ethernet frame transfer process, interrupt handling at either end includes three different entities. Firstly, the interrupt response mechanism of the CPU core, followed by the processing of interrupt response with the requirements of the operating system, and then the PCIe hardware device also has a set of specifications for sending interrupts to the CPU operating system. The interrupt handling mechanism of either party can be described in lengthy text, which will not be further elaborated in this article.

The 216DB61 HESG324063R100J bus supports two interrupt modes, the traditional INTx interrupt and the interrupt request mechanism based on memory write requests, namely message interrupts. The design scheme in this article uses traditional INTx interrupts. For the convenience of description, we describe the interrupt processing flow from the perspective of FPGA timing diagram, which is specifically divided into the host (interrupt signal sent by PCIe to the host), PCIe hard core, interrupt enable signal configured by the driver, and interrupt source on the 216DB61 HESG324063R100J  side. The following diagram shows the interrupt interaction process between the FPGA development board and the host when the host operating system is VxWorks.

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