216EA62 1MRB150083R1F 1MRB178066R1F | ABB| PCIe IP Core Configuration MODULE

Description

216EA62 1MRB150083R1F 1MRB178066R1F | ABB| PCIe IP Core Configuration MODULE

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There are three interrupt sources on the 216EA62 1MRB150083R1F 1MRB178066R1F side that can trigger interrupts, namely DMA write start, DMA write completion, and DMA read completion interrupts. Among them, the write start interrupt source is when the FPGA informs the host that there is data to be uploaded through DMA write operations; The write completion interrupt is when the FPGA encapsulates all data into a DMA write request packet; The read completion interrupt is when the FPGA has received all DMA read completion packets from the host. The position “1” in the above figure indicates that the interrupt source mwr_start_interrupt has been raised.

If any interrupt source is raised, the 216EA62 1MRB150083R1F 1MRB178066R1F will configure the “set interrupt” timing for the PCIe IP core. After a successful handshake between cfg_interrupt and cfg_interrupt_rdy, if cfg_interrupt_1ssert is high, it is set as an interrupt. (cfg_interrupt is an interrupt request sent by the PCIe hard core to the host, and cfg_interrupt_rdy is the response received by the host after receiving the interrupt request. At this time, it is necessary to check the status of cfg_interrupt_1ssert. If it is high, it is set as an interrupt, as shown in “2” in the above figure; if it is low, it is clear as an interrupt request, as shown in “5” in the above figure.)
After a period of 216EA62 1MRB150083R1F 1MRB178066R1F (approximately 17 clocks in this case), the hard interrupt level INTA on the host side is raised, and it is only then that the FPGA board truly sends an interrupt to the host. As shown in “3” in the above figure.

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