8610-FT-NA | EATON | Generate interrupt timing module

Description

8610-FT-NA | EATON | Generate interrupt timing module

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From the above figure, 8610-FT-NA  can be seen that the read completion interrupt mrd_one_interrupt triggers the set interrupt timing. The hard interrupt level of the host is raised, and the driver writes “1” to the highest bit of the control and status register 04H (int_dis_o signal shown in the figure) PIO operation to turn off the interrupt function. At this time, the hardware does not generate the set interrupt timing until the driver jumps out of the interrupt reset program and writes “0” to the int_dis_o of 04H to enable the interrupt; The driver PIO reads the interrupt status register (blue line 1 in the diagram) and samples it to the completion of the read (mrd_dond_interrupt signal in the diagram). The interrupt flag is set to 1. The hardware generates a clear interrupt timing and lowers the hard interrupt level on the host side. Note that at this point, the write start interrupt (mwr_start_interrupt signal in the diagram) is just raised.

The 8610-FT-NA only records the completion of the read interrupt and resets the completion of the read interrupt flag (blue line 2 in the diagram), Then the driver executes the read completion interrupt state machine, and after jumping out of the read completion interrupt state machine, the driver re enables the interrupt (blue line 3 in the diagram). At this time, the hardware side is allowed to 8610-FT-NA  a set interrupt timing because of the write start interrupt. The driver detects that the hard interrupt level signal is high again, and the PIO read interrupt status register (blue line 4 in the diagram) samples the write start interrupt flag as 1. The hardware generates a clear interrupt timing, Lower the hard interrupt level on the host side, drive to record the start of write interrupt and reset the start of write interrupt flag (blue line 5 in the diagram), then drive to execute the start of write interrupt state machine.
In the second testing scenario, 8610-FT-NA  can determine the minimum time interval between two adjacent interrupts by counting. The hardware side generates the first interrupt segment timing (blue line 1 in the diagram). After executing the first interrupt, the driver side lowers int_dis_o and re enables the interrupt. The hardware side immediately generates a set interrupt timing for the second interrupt operation

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