FB201 | KEBA | Simulation waveform module

Description

FB201 | KEBA | Simulation waveform module

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FB201 is the simulation waveform diagram of the top module of the register after the third mock examination redundancy reinforcement. The state of the circuit at the marking line in the figure is wrong (it can be seen from the input d that the correct state should be output to 7 after the third rising edge of the clock). The reason is that TMR_DFF is a combined logic output. At the first rising edge, when the input D of reg0 is sampled by clk, clk_skew [1], out [0] becomes 1, and the input out [0] of reg1 is sampled by clk_skew [0] After sampling, its q2 (signal in the circuit shown in FB201 ) becomes 1, and the circuit state remains 1. When the second rising edge comes, due to the fact that q2 of reg1 is already 1, the input output 1 of reg2 becomes 1 after clk sampling, and after majority voting, out1 becomes 1, and the circuit state is 3. After the input output 1 of reg2 is sampled by clk_skew [1], clk_skew [0], its q1 and q2 become higher, and the output output output 2 becomes higher, and the circuit state becomes 7, resulting in a state error.

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