FBM201 P0914SQ | FOXBORO | Gate level netlist module

Description

FBM201 P0914SQ | FOXBORO | Gate level netlist module

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The function of  FBM201  synthesis is to read the designed RTL code and, based on timing constraints, synthesize the RTL code to the structure level to generate a mapped gate level netlist. One important step is to specify the synthesis library used, which is generally provided by the chip manufacturer. The library contains information such as pin to pin timing, area, pin type, and power consumption, The units in the synthesized gate level netlist are the units defined in the library.

The reinforcement process of the third mock examination redundancy is actually to generate two redundant triggers for each trigger in the design and add voting logic, which cannot be reflected in the FBM201  code. Therefore, we can modify the gate level netlist after the original design is integrated, change the trigger to the third mock examination redundant trigger, and use the gate level description to write the the third mock examination redundant trigger module, Then, it can be integrated with the modified netlist again to get the netlist file after the third mock examination redundancy reinforcement. It is worth noting that there are many types of triggers in the DC comprehensive library, such as SDFF, EDFF, SEDFF, JK, DFF. Even if only DFF triggers are limited in the comprehensive script, there will be several types. Therefore, corresponding the third mock examination redundant trigger modules should be written for different units (their structures are shown in Figure 1). In addition, due to the presence of three clock signals, a clock generation module needs to be developed, whose function is to generate two clock signals with mutual delays by FBM201  .

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