FBM201d P0922YK | FOXBORO | Example Comprehensive Library module

Description

FBM201d P0922YK | FOXBORO | Example Comprehensive Library module

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Firstly, the original FBM201d  code was synthesized using the synthesis tool DsignCompiler in Synopsys to obtain the gate level netlist of the circuit. The circuit in the gate level netlist is actually described by instantiating the unit of the synthesis library to describe the structure of the circuit. Formal validation tool Formality can be used to verify whether the RTL code and the synthesized gate level netlist are functionally consistent.

Then modify the FBM201d  level netlist, add the line network type ck [2:0] in the netlist, and instantiate the clkgen module. Then change the trigger in the netlist to a the third mock examination redundant trigger, and modify its clock port to {clk, ck [1:0]}. Since the comprehensive database does not contain these two modules, then there are two modules in the netlist that are not processed by the FBM201d  tool, the clock generation module and the the third mock examination redundant trigger module, The modified netlist is not a fully mapped gate level netlist.

Finally, the modified netlist, the clock generation module and the the third mock examination redundant trigger module are integrated again. This integration is actually the integration of the clock generation module and the the third mock examination redundant trigger, mapping them into units in the comprehensive library, and the gate level netlist obtained is the gate level netlist designed after the third mock examination redundancy reinforcement.

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