FBM201e P0924TR | FOXBORO | Redundant trigger module

Description

FBM201e P0924TR | FOXBORO | Redundant trigger module

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Since the clock port of the the third mock FBM201e  redundant trigger unit has three bits, even if the unit of the the third mock examination redundant trigger is added to the library, the synthesizer cannot directly map the design to this unit, so the clock generation module can be placed inside the FBM201e , so the clock port of the the third mock examination redundant trigger is only one bit, and the trigger unit is replaced with the corresponding the third mock examination redundant trigger unit in the library file, DC can directly map the triggers in the circuit to FBM201e  , and the design can be completed in one synthesis. However, this will increase the area of the entire chip significantly (the clock generation module is no longer shared). In addition, the above method can also be used to modify the netlist after the original design synthesis.

As mentioned earlier, there are many types of triggers in the library file, so corresponding library units should be established for different DFF triggers. Below is a method for establishing library units, which mainly consists of two steps: layout design and simulation feature extraction.

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