FBMSVH | FOXBORO | Digital signal processing module

Description

FBMSVH | FOXBORO | Digital signal processing module

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An example of a filter is shown, which, without considering other sources of error, limits mirror frequency suppression to approximately 60dB at 10MHz (20MHz bandwidth). However, before 30MHz, it effectively reduces mirror frequency suppression by another 30dB. This type of filter and ADC using digital signal processing to correct the gain and phase error of the mixer may improve the results by about 30dB. Some signals (such as WCDMA) have a relatively high tolerance for poor mirror frequency suppression, while others (such as GSM) OFDM and high-order QAM do not.

The launch of high-speed ADCs with 100dB SFDR, such as the 16 bit 130Msps LTC2208, means that normal operation may also be maintained in the presence of very strong interference signals. FBMSVH, but mirror frequency suppression close to this level will require extraordinary measures. It is understandable to expect a large bandwidth in direct conversion, as at a given sampling rate, the bandwidth provided by using orthogonal signals for mirror frequency suppression processing may be twice the bandwidth of IF sampling receivers. In the case of IF sampling (undersampling), high bandwidth and low-pass ripple typically require high center frequencies, which in turn limits the dynamic range of many ADCs and amplifiers, or at least results in high power consumption of the driving amplifier. The actual IF filter is reasonably limited to approximately 20% of the center frequency. The increasingly common target of 100MHz available bandwidth means 500MHz IF and sampling rates exceeding 200Msps, which leads to higher power consumption. However, high-speed ADCs with an analog input bandwidth of 1GHz, such as the 14 bit 250Msps LTC2152-14, provide good undersampling performance for these high input frequencies and only consume 300mW of power.

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