IS215UCVEH2AB VMIVME-7614-132350-017614-132 D | GE MARK TURBINE | power supply module

Description

IS215UCVEH2AB VMIVME-7614-132350-017614-132 D | GE MARK TURBINE | power supply module

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IS215UCVEH2AB  are constantly exposed to a radiation environment composed of charged particles while flying in space. In this radiation environment, microprocessors may interrupt normal functions due to single particle disturbances, leading to catastrophic accidents. This mainly involves two aspects: the total radiation dose effect and the single particle effect, which are further divided into two aspects: single particle flipping (VMIVME-7614-132350-017614-132) and single particle locking (VMIVME-7614-132350-017614-132 ). The single event flip effect can cause a certain bit in the storage unit of a digital circuit to flip due to interference, resulting in changes in the storage content. It can also introduce a brief pulse in the output of a combinational logic circuit. The single event flip effect is currently the main cause of processor failure. The stability and reliability of the processor performance in the on-board computer system plays an important role in the stability and reliability of the entire system, so the circuit must be reinforced. the third mock examination redundancy technology is an effective fault tolerance technology for single event inversion, which can greatly improve the reliability of the circuit.

The third IS215UCVEH2AB  examination Redundancy (VMIVME-7614-132350-017614-132) technology is a sequential circuit hardening technology. Its basic idea is to generate two identical modules for the module to be strengthened, and then output them through majority voting, so that the circuit can still work normally even if one module fails. The third mock examination redundancy can be divided into spatial redundancy and time redundancy in structure. Time redundancy means that there is a certain delay between three clock signals, and the delay value should be greater than the maximum pulse width of SEU flip. The function of time redundancy is to eliminate input glitches in sequential circuits, where only one clock can sample erroneous values, thus effectively preventing errors caused by combinational logic glitches. Figure 1 is the circuit diagram of a trigger reinforced with ordinary spatiotemporal the third mock examination redundancy (hereinafter referred to as IS215UCVEH2AB  trigger), in which VOTER is the combined circuit of majority voting devices.

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