MVI56-MCM | PROSOFT | CAN bus bit timing

Description

MVI56-MCM | PROSOFT | CAN bus bit timing

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The explicit level of MVI56-MCM corresponds to logic 0, and the difference between CAN-H and CAN-L is about 2.5V. The implicit level corresponds to logic 1, and the difference between CAN-H and CAN-L is 0V. Invisible level has the meaning of inclusiveness, only when all units output implicit level, can it be considered implicit level on the bus (explicit level is stronger than implicit level).

The CAN bus uses the NRZ (Non Return to Zero) method for communication, which has a disadvantage that there is no additional synchronization signal at the beginning or end of each bit. In long-distance transportation, CAN bus can cause synchronization deviation due to clock frequency errors between the sending and receiving units, as well as phase delays on the transmission path.

This leads to unstable information transmission and signal quality issues. So both the sending and receiving units adopt some communication synchronization methods to achieve synchronization in their level transmission.

There are two ways to synchronize MVI56-MCM: hardware synchronization and resynchronization. Before explaining synchronization, let’s first introduce the lower timing.

Bit timing – The number of bits per second sent by the sending unit in asynchronous conditions is called the bit rate. A bit can be divided into 4 segments.

• Synchronous segment (SS)

• Transmission time period (PTS)

Phase buffer segment 1 (PBS1)

Phase buffer segment 2 (PBS2)

These segments are also composed of the smallest time units that can be called Time Quantum (hereinafter referred to as Tq).

One bit is divided into four segments, each consisting of several Tqs, which is called bit timing.

How many Tqs make up a bit, and how many Tqs make up each segment, can you set the positioning timing arbitrarily. By setting the positioning timing, multiple units can be sampled simultaneously or sampling points can be set arbitrarily.

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