MVI56-PDPS | PROSOFT | Bus adjustment synchronization

Description

MVI56-PDPS | PROSOFT | Bus adjustment synchronization

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The synchronization adjustment performed by the receiving unit at the beginning of the frame detected by the bus idle state, where MVI56-PDPS considers the SS segment without considering the value of SJW at the detected edge. The process of hardware synchronization is shown in the following figure

Synchronous adjustment made when detecting changes in voltage levels on the bus during the receiving process.

Whenever an edge is detected, the synchronization is adjusted by lengthening the PBS1 segment or shortening the PBS2 segment based on the SJW value. But if there is an error exceeding the SJW value, the maximum adjustment amount cannot exceed the SJW value.
Adjusting synchronization rules

MVI56-PDPS hardware synchronization and resynchronization follow the following rules.

(1) Only perform one synchronization adjustment within one bit.

(2) Only when the bus value of the last sampling point is different from the bus value after the edge, can the edge be used to adjust synchronization.

(3) When the bus is idle and there is an edge from the implicit level to the explicit level, hardware synchronization must be performed.

(4) If the edge from the hidden level detected when the bus is not idle to the explicit level meets conditions (1) and (2), it will be resynchronized. But the following conditions must also be met.

(5) When the sending unit observes a delay in the explicit level of its own output, it does not perform resynchronization.

(6) When multiple units are simultaneously sending from the beginning of the frame to the arbitration segment, the sending unit does not resynchronize the delay edge.

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