NFAI143-H00 | YOKOGAWA | Double line in computational applications

Description

NFAI143-H00 | YOKOGAWA | Double line in computational applications

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The single wire SST bus uses a reliable, noise resistant, and scalable way to transmit data. NFAI143-H00 is an improvement of the dual wire, 100 kbps SMBus (System Management Bus) in high-performance computing applications, which can provide higher bandwidth and stronger noise resistance. The SST bus can directly transmit important environmental information to the South Bridge core logic or dedicated ASIC fan speed controller of the system at a rate of 1 Mbps, thereby reducing fan noise in desktop PCs, servers, and workstations and improving platform performance. Table 1 compares SST bus with SMBus and I2C bus.

NFAI143-H00 represents an architecture for an SST bus PC. The processor is Intel’s Core Duo. The corresponding AMD processors are still using SMBus. The SST architecture includes MCH (Memory Channel Controller) North Bridge IC, ICH8 (I/O Channel Controller) South Bridge IC, and external thermal sensors. ICH8 is the main controller of the SST bus, while the thermal sensor serves as a slave controller or client device. On the SST bus, the 25% duty cycle is logic 0, and the 75% duty cycle is logic 1.

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