T8461 | ICS TRIPLEX | Redundant configuration controller

Description

T8461 | ICS TRIPLEX | Redundant configuration controller

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T8461 shows the effect of redundancy methods on repair rate, categorized by all designs, all analysis layers, memory, blocks, and by layer or group. Figure 3 is a graph created by a tool that shows the average number of failures for each redundant configuration and various types of defects. A combination of a redundant row and a redundant column can greatly reduce the average number of failures, while increasing resources has little effect. From these results, it can be concluded that the expected average number of failures depends on the considered memory layout, as well as the defect density of the wafer factory and process. Now, designers can determine the effectiveness of various redundant configurations based on the expected yield rate of an embedded memory.

Based on this T8461 information, Calibre calculates the average number of failures in non redundant memory and various redundant configurations. Figure 1 presents the results in the form of a table, including the average number of failures for different redundant configurations. The rows in the table display the entire design (memory only) and the results of specific types of defects. The highlighted line indicates a significant improvement in the average failure rate of the 1024 x 32-bit storage core; The failure rate in column 6 is half of that in column 5. To achieve this improvement, the sixth column contains a redundant row, but adding a second redundant row results in almost no further improvement (column 7).

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