TRICONEX 3201 | TRICONEX | Accessing Memory module

Description

TRICONEX 3201 | TRICONEX | Accessing Memory module

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The decision TRICONEX 3201 of the scheduler takes exactly 3 eTPU cycles. For processors running at a system frequency of 100MHz (neither the maximum nor minimum frequency between processors equipped with eTPU), event service can start 60 nanoseconds after the event occurs. This is much faster than the interrupt delay in the CPU. On the contrary, when multiple service requests are issued simultaneously, this time may be much longer. Good eTPU functionality should not spend too much time on one channel’s service to ensure that it does not delay other channels. TRICONEX 3201 that require very strict time requirements should be scheduled and organized as several services for different events or several services for a single event.

In addition to arithmetic logic units, the eTPU micro engine also includes a multiplication and division unit, making the eTPU more powerful. The basic integer size of the eTPU micro engine is 24 bits. One eTPU cycle occupies two CPU clock cycles. An eTPU instruction can be used to access memory or serve channel hardware for arithmetic operations.

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