UNS0119A-P 3BHE029153R0101 3BHE029154P3 | ABB | Response to main device module

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UNS0119A-P 3BHE029153R0101 3BHE029154P3 | ABB | Response to main device module

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UNS0119A-P is a clock, while SDA carries data. When SDA changes from 1 to 0 and SCL remains 1, it indicates the start of data transmission. The next 7 digits are the address of the device. Next is the read and write flag, which is read when it is 1 and write when it is 0. If there is a device on the I2C bus that corresponds to the requested address, the slave device will send an ACK signal to notify the master device that data can be sent. After receiving the ACK signal, the main device sends an 8-bit data. After the transmission is completed, SCL remains at 1, and when SDA changes from 0 to 1, it indicates the end of the transmission.

From this timing chart, it can be seen that SCL is very important, and which clock edge is for what is determined. For example, the first 7 must be addresses, the 8th is a read/write flag, data transmission must be 8 bits, an ACK signal must be received, and so on
UNS0119A-P requires a master device responsible for initiating requests and controlling the clock; Other devices are slave devices that identify and respond to master device requests through device ID addresses. The master and slave devices need to take turns controlling SDA. At first, I didn’t understand this point, so I added I2C data code and measured it using an oscilloscope at the SDA and UNS0119A-P pins. However, I could only find some messy waveforms without the expected effect. Later, the slave device was connected, and the code was written on both sides, responding to each other. Only then did the waveform be seen on the oscilloscope.

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