XDD501A101 3BHE036342R0101 | ABB | High level state module

Description

XDD501A101 3BHE036342R0101 | ABB | High level state module

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XDD501A101 requires a master device responsible for initiating requests and controlling the clock; Other devices are slave devices that identify and respond to master device requests through device ID addresses. The master and slave devices need to take turns controlling SDA. At first, I didn’t understand this point, so I added I2C data code and measured it using an oscilloscope at the SDA and SCL pins. However, I could only find some messy waveforms without the expected effect. Later, the slave device was connected, and the code was written on both sides, responding to each other. Only then did the waveform be seen on the oscilloscope.

From the graph, it can be seen that the timing is as follows:
Initiated by the host, when XDD501A101 is at high level, SDA undergoes high to low shear, forming a start signal;
Next are the 7-bit address and a read-write flag. Here, the 7-bit address is 0111100, which is 0x3c, which is the address ID set in our code; The last digit of 0 indicates a write operation;
Next, at the next clock, the master releases the SDA in a high-level state, and the slave responds by pulling the SDA down;
Next are two 8-bit data XDD501A101 and the response, which is 0x2E, which is the ASCII code with the “.” symbol and matches the expected output;
There are other data and the last stop bit, which have been truncated in the figure.

Mailbox：sauldcsplc@gmail.com |XDD501A101 3BHE036342R0101
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